Static random access memory (SRAM) stores “0” or “1” information for a formed latch by cross-coupled inverters with positive feedback characteristics in a memory cell. Referring to FIG. 1, the structure of a memory cell of the currently common static random access memory is composed of six transistors. FIG. 1 shows a circuit structure diagram of one memory cell of common static random access memory, and the circuit structure of the six transistors mentioned above has symmetry and comprises a first pass-gate transistor (PG1), a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pass-gate transistor (PG2), a second pull-up transistor (PU2) and a second pull-down transistor (PD2) connected between a first bit line (BL) and a second bit line (BLB). The first pull-up transistor (PU1) and the first pull-down transistor (PD1) form a first inverter, the second pull-up transistor (PU2) and the second pull-down transistor (PD2) form a second inverter, and the first inverter and the second inverter are cross-coupled, that is, an input end of the first inverter is electrically connected to an output end Nb of the second inverter, and an output end Na of the first inverter is electrically connected to an input end of the second inverter so as to form a latch for locking data logic values. The gates of the first pass-gate transistor (PG1) and the second pass-gate transistor (PG2) and the word line are in connection, and respectively control the connection or disconnection of the first inverter and the second inverter to or from the first bit line (BL) and the second bit line (BLB) when performing read/write operations on the SRAM memory.
The static random access memory is an extremely important part in the IC field, and its testing work has important practical application value for ensuring the quality of integrated circuit products. Traditional voltage test-based testing method has been widely applied; however, this method still may not effectively detect certain faults, and as a complement to the voltage testing method, the current testing method can improve fault coverage and product reliability.
Testing the reading current of the static random access memory can effectively screen out abnormal static random memory cells. However, the current existing testing steps for reading current of the static random access memory are complicated, and a large number of leads need to be used in the test, such that a great deal of time is consumed and it is not suitable for batch testing. Specifically, when the current existing method for testing reading current of the static random access memory is tested, signals firstly need to be written by the first bit line (BL) and the second bit line (BLB), then a voltage is applied to the BL and the BLB, and finally the BL and BLB measure the current, and the reading current of the static random access memory is current at a higher current end in two ends of the BL and BLB. In the prior art, the testing method for reading current needs a relatively large number of testing keys and pins as well as a longer testing time to obtain a sufficient amount of testing data for detecting abnormal changes in the memory cell.
Therefore, there is an urgent need for a testing method for reading current of static random access memory cell to reduce the hardware devices required for the test and make the steps simple, and make it convenient for a tester to test static random access memories in batches.